2.5D/3D Packaging Archives - ACM Research, Inc.

Tackling Flux Cleaning Challenges in Panel-Level Packaging

Multi-reticle packages – optical devices with multiple reticle patterns that are user-switchable as needed – are becoming increasingly common as hyper-scale computing and other applications such as artificial intelligence (AI) adopt 2.5D to 3.5D device packaging. The advanced packaging industry, in turn, is implementing larger, panel-level packaging (PLP) to improve yield and increase throughput for […]

Panel-Level Packaging Will Enable Chiplet Packaging Advancements

The 3D packaging sector has been growing rapidly, driven by the expansion of chiplet packaging across the ecosystem. Chip and package sizes have also grown rapidly as 2 x 800mm2 chips are being placed in a single package along with high-bandwidth memory (HBM). Demand for these large chiplets has generated supply constraints due to how […]

Stress-Free Polishing: The Final TSV Optimization Step

Throughout this blog series, we’ve taken you on a journey through the various steps involved in developing and optimizing through-silicon vias (TSVs), which have become vital to packaging of many types of devices that require smaller-footprint, higher-density package stacks. Part 1 discussed TSV formation and the benefits of our SAPS™ megasonics for TSV cleaning; Part […]

PECVD: A New Approach for Eliminating TSV Gaps

ACM Research provides an advanced solution for dealing with TSV Gaps using Plasma Enhanced Chemical Vapor Deposition (PECVD) Welcome to part three of our blog series on optimizing through-silicon vias (TSVs), vertical interconnect structures vital to heterogeneous integration of multiple components for 2.5D/3D packaging techniques. Part one provided an introduction to the TSV formation process […]

Electroplating of Metal for TSV Formation

Part one of this blog series on optimizing wafer-level through-silicon vias (TSV) for heterogeneous integration of multiple components and 2.5D/3D packaging provided an overview of the TSV formation process and elucidated post via cleaning solution. The SAPS™ megasonic technology developed by ACM Research enables chipmakers to remove residue following TSV formation much more effectively and completely […]

Through Silicon Via (TSV) for Heterogeneous Integration

While heterogeneous integration of multiple components and 2.5D/3D packaging techniques pair perfectly with complex stacking architectures, these technologies elicit high demands on device manufacturing processes. Through-silicon via is the key enabler, allowing direct chip-to-chip connection through the chip stack without requiring wire bonding or edge wiring. The growing demand for miniaturized semiconductor chips and their […]