October 29, 2026 ~ Part 1 of this series examined cleaning challenges associated with panel-level packaging (PLP) and manufacturing. This installment goes into some of the key industry and market drivers spurring PLP demand. Multi-reticle packages are growing at a rapid rate. Figure 1 shows TSMC’s advanced packaging roadmap growing from 5.5 reticles today to 14 reticles in 2029 […] Read More
Blogs and Articles
September 17, 2026 ~ Advances in automotive, high-performance computing (HPC), artificial intelligence (AI) and medical technology are heightening demand for heterogeneous integration. As a result, the semiconductor packaging industry is being driven to develop large multi-reticle packages. To process the massive amounts of data being generated, chip and package sizes have grown significantly. Chip sizes are using the full […] Read More
July 24, 2026 ~ While it might not receive as much attention as extreme ultraviolet (EUV) lithography, wet wafer cleaning and surface preparation remains one of the most critical processes in semiconductor manufacturing. Device reliability, yield and long-term performance are all directly linked to wafer cleanliness as devices pass through hundreds of process steps including deposition, implantation, polishing, etching, patterning, and interconnect process steps. Even a single particle or trace […] Read More
July 22, 2026 ~ It’s not news that artificial intelligence (AI) is driving larger and larger chip packages. Nvidia’s Blackwell architecture helped define the rapid move toward multi-reticle packages for generative AI chips; its Blackwell B200 superchip is essentially a massive dual-die processor (2 x 800mm2 for total area of ~1600mm2), built to the reticle limit of 208 billion transistors.1 A round 300mm wafer can fit about 64 800mm2 chips, but since the chip is square and the wafer is round, a significant […] Read More
June 23, 2026 ~ Welcome to Part 3 of our blog series on optimizing through-silicon vias (TSVs), vertical interconnect structures vital to heterogeneous integration of multiple components for 2.5D/3D packaging techniques. Part 1 introduced the TSV formation process and post-via cleaning, and Part 2 delved into the role electroplating plays in TSV creation. In this installment, we look at […] Read More
June 11, 2026 ~ Wafer cleaning is one of the most critical steps in the semiconductor process flow, especially as dimensions continue to shrink to below the 1-nanometer (nm) node. Photoresist residue and particulates can reduce yields in large-die AI chips, impacting the performance of the final product or causing the chips to be scrapped. The sulfuric acid hydrogen peroxide step, or sulfuric peroxide mixture (SPM), is essential for removing organic contaminants from post-etch substrates and ion-implanted films, as well as for platinum silicide residue removal. SPM processes traditionally have been performed in tanks […] Read More
May 18, 2026 ~ Following the launch of our ACM Planetary Family™, which brings together a process-aligned portfolio for semiconductor manufacturing, we delve deeper here into each of the planet series and how they reflect our product lines. Our offerings are grouped into eight different series that represent the essential stages in front-end and advanced packaging, providing a clearer path to identifying the right solutions for specific needs. With this approach, customers can more easily find the […] Read More
May 6, 2026 ~ As the feature sizes and critical dimensions of logic, memory and analog semiconductor devices shrink with advanced technology nodes, the sensitivity to submicron contaminants has increased significantly. Consequently, the use of wet cleaning technology to remove particulates and contaminants is critical to the success of semiconductor manufacturers. Single-wafer and batch cleaning technologies are both used […] Read More
April 3, 2026 ~ One of the most important shifts in semiconductor manufacturing today is not just the continued growth of wafer-level packaging (WLP), but the increasing reliance on enabling, highly specialized process technologies. As device architectures evolve toward heterogeneous integration (HI) and chiplet-based designs, key technologies such as wet processing, electrochemical plating (ECP), plasma-enhanced chemical vapor deposition (PECVD), […] Read More
February 17, 2026 ~ Silicon carbide (SiC) and gallium nitride (GaN) are becoming mainstream within the semiconductor industry due to material properties that make them ideal for multiple applications. These properties—ranging from high thermal conductivity and mechanical strength to optical refractive index control—have made SiC and GaN suitable candidates for multiple end products. Some key applications include power and […] Read More