Tackling Flux Cleaning Challenges in Panel-Level Packaging

Multi-reticle packages – optical devices with multiple reticle patterns that are user-switchable as needed – are becoming increasingly common as hyper-scale computing and other applications such as artificial intelligence (AI) adopt 2.5D to 3.5D device packaging. The advanced packaging industry, in turn, is implementing larger, panel-level packaging (PLP) to improve yield and increase throughput for […]

Panel-Level Packaging Will Enable Chiplet Packaging Advancements

The 3D packaging sector has been growing rapidly, driven by the expansion of chiplet packaging across the ecosystem. Chip and package sizes have also grown rapidly as 2 x 800mm2 chips are being placed in a single package along with high-bandwidth memory (HBM). Demand for these large chiplets has generated supply constraints due to how […]

AI Spurring Growth of Panel-Level Packaging

It’s not news that artificial intelligence (AI) is driving larger and larger chip packages. For example, Nvidia’s Blackwell architecture is what is called a two-reticle package1, meaning that the chips each have an area of approximately 800mm2. Building chips and packages of this size poses myriad challenges – one of which is how many 800mm2 […]

PECVD: A New Approach for Eliminating TSV Gaps

ACM Research provides an advanced solution for dealing with TSV Gaps using Plasma Enhanced Chemical Vapor Deposition (PECVD) Welcome to part three of our blog series on optimizing through-silicon vias (TSVs), vertical interconnect structures vital to heterogeneous integration of multiple components for 2.5D/3D packaging techniques. Part one provided an introduction to the TSV formation process […]

Championing Environmental Sustainability Through Local SOLVE Oregon Clean-Up Initiatives

Environmental responsibility isn’t just a tagline at ACM Research, it’s a core principle woven into the fabric of our company. We take pride in developing innovative solutions for the semiconductor industry, but we also recognize the importance of protecting the planet for future generations. During Earth Month, our Oregon team proudly collaborated with SOLVE Oregon, […]

Electroplating of Metal for TSV Formation

Part one of this blog series on optimizing wafer-level through-silicon vias (TSV) for heterogeneous integration of multiple components and 2.5D/3D packaging provided an overview of the TSV formation process and elucidated post via cleaning solution.  The SAPS™ megasonic technology developed by ACM Research enables chipmakers to remove residue following TSV formation much more effectively and completely […]

Through Silicon Via (TSV) for Heterogeneous Integration

While heterogeneous integration of multiple components and 2.5D/3D packaging techniques pair perfectly with complex stacking architectures, these technologies elicit high demands on device manufacturing processes. Through-silicon via is the key enabler, allowing direct chip-to-chip connection through the chip stack without requiring wire bonding or edge wiring. The growing demand for miniaturized semiconductor chips and their […]

SiC Challenges Equipment Manufacturers

Silicon carbide (SiC) substrate-based chips are on the (very) fast track due to SiC challenges. The automotive industry wants SiC chips so it can increase electric vehicle (EV) range and decrease charging time. The telecom industry wants them for 6G. And the renewable energy folks want them for more efficient power generation and storage. The […]