AI Spurring Growth of Panel-Level Packaging

November 26, 2024

panel-level packaging

It’s not news that artificial intelligence (AI) is driving larger and larger chip packages. For example, Nvidia’s Blackwell architecture is what is called a two-reticle package1, meaning that the chips each have an area of approximately 800mm2. Building chips and packages of this size poses myriad challenges – one of which is how many 800mm2 chips can fit on a 300mm wafer.

With a chip size of ~800mm2, you can fit approximately 64 chips on a round 300mm wafer. However, this does not consider yield. As the chip is square and the wafer is round, a significant amount of silicon goes to waste in processing the chip.

When it comes to wafer-level packaging (WLP) or fan-out wafer-level packaging (FOWLP), you run into the same problem. You are limited by the area of the silicon wafer, thus causing throughput and yield problems during the packaging process. TSMC’s chip-on-wafer-on-substrate (CoWoS), the current method of packaging Nvidia’s advanced chips, has capacity and yield constraints, according to TSMC earnings calls.

FOPLP (Fan-Out Panel-Level Packaging) Enables System Package Creation

Given these challenges, fan-out panel-level packaging (FOPLP) has attracted interest and attention from the semiconductor industry. To help solve the packaging side of the supply chain constraint, packaging manufacturers have proposed using square substrates, typically made of glass, to introduce a new method of packaging the wafers on a panel that increases the number of chips you can process at once.

The industry, for now, has settled on panel sizes of 515mm x 510mm, which has 3x the area of a 300mm silicon wafer; and 600mm x 600mm, which has 5x the area of a 300 mm wafer2 (Figure 1). Intel, Samsung, and some outsourced assembly and test (OSAT) companies are also moving toward panel-level packaging (PLP). This is due mainly to the growth of AI chip packages, which, as they continue to grow increasingly larger, are becoming systems, rather than individual packages placed upon a printed circuit board (PCB).

Panel-Level Packaging Figure

Figure 1. A 300mm wafer compared to 515mm x 510mm and 600mm x 600mm panels. (Source: ACM Research)

Tackling panel-level packaging bevel etch and clean

The transition to Panel-Level Packaging (PLP) will create new processing challenges that will require a new set of tools. Cleanliness and thickness at the panel edges are critical for yields and processing. Contamination or a raised edge bevel can create issues for lithography, deposition, and bonding and can potentially generate stress, which can cause warpage across the panel.

The ability to clean effectively across an entire panel to remove flux residues and particles will also be a critical part of the move to PLP. This requires proper handling of the panel as well as ensuring it is dry before the next process steps take place. The deposition and removal of metals for redistribution layers (RDLs), pillars, and bumps will play an important role in the creation of both the RDLs and the chiplets.

As a company that enables advanced WLP with our cleaning and deposition equipment, ACM Research recently introduced three new tools to address the industry’s move to PLP. Given our expertise in both cleaning and electrochemical plating, these tools fit seamlessly into our portfolio and will help our customers move from WLP to PLP technology.

  • Ultra C bev-p panel bevel etching tool – Designed specifically for panel substrates, Ultra C bev-p offers compatibility with organic, glass, and bonding panels. The system enables advanced panel handling with a single robot, efficient copper removal using diluted sulfuric acid and peroxide (DSP), and high throughput of 40 panels per hour.
  • Ultra C vac-p flux cleaning tool – This tool addresses critical steps in the advanced packaging process on organic and glass panels, particularly removal of flux residue before underfilling, which is essential for eliminating voids. Its vacuum technology ensures cleaning liquid reaches all gaps, even in large panel substrates where traditional methods fall short.
  • Ultra ECP ap-p tool – Our panel-focused electrochemical plating (ECP) tool supports 515mm x 510mm glass and organic panels, with an option to expand to 600mm x 600mm. Its horizontal plating approach achieves superior uniformity and precision across the entire panel, and its advanced automation features enhance manufacturing efficiency and quality control.

Our new tools are designed to work together to meet emerging PLP requirements, including multiple-reticle PLP, to help the industry quickly move forward in the transition from WLP.

Panel Level Packaging FAQ  

What limitations exist with wafer-level packaging (WLP) and fan-out wafer-level packaging (FOWLP)?

The scalability of WLP is constrained both by wafer size and shape, as they restrict the maximum number of dies processed per wafer. WLP mainly supports single-die solutions, limiting multi-chip integration on one package. Warpage or bending of the wafer during processing is a persistent issue that affects yield and reliability. In addition, the exposed sides of the die remain vulnerable to chipping and cracking after dicing, posing handling risks. WLP also generally requires specialized tools and processes, increasing manufacturing complexity.

FOWLP allows the WLP redistribution layer (RDL) and interposer area to exceed the die size, maintaining the thin profile while enabling more I/O connections and better electrical performance. However, while improving on WLP, FOWLP faces higher warpage due to the larger reconstituted wafer stack, which can reach significant levels and complicate handling and placement precision. Warpage can decrease yield and reliability if not properly controlled. Additionally, the FOWLP process involves complex steps that can increase production complexity and cost, making material selection and process control critical to performance.

What is fan-out panel-level packaging (FOPLP), and why is it gaining traction?

FOPLP uses larger rectangular panels instead of circular wafers to carry and package ICs, using redistribution layers to integrate multiple heterogeneous components into a single package. FOPLP offers significant cost savings through higher throughput and better utilization of materials, resulting in up to 20–30% lower costs compared to FOWLP. The process features improved electrical performance, thinner profiles, and shorter interconnects, benefiting such high-performance and miniaturized devices as smartphones, wearables, automotive electronics, and IoT applications. Additionally, FOPLP enables better scalability for volume manufacturing and supports heterogeneous integration – key to advanced semiconductor packaging.

Which companies are moving toward PLP?

A number of companies have made public their plans to integrate PLP and FOPLP into their packaging strategies targeting advanced chip development. Prime examples include TSMC, Samsung, ASE and Amkor Technology.

What are the key processing challenges with PLP?

Key processing challenges with PLP include maintaining cleanliness across large panel surfaces, controlling and minimizing warpage and raised edge bevels, and ensuring uniformity in critical process steps such as electroplating, lithography, and bonding. The larger panel sizes also introduce complexity in handling, bringing contamination risks that can impact yield. Other major concerns include achieving consistent die placement, managing mold material shrinkage during curing, and die shifting on the panel. Variations in panel size and materials also demand specialized process tool adaptations, and industry standardization is being investigated to improve design-to-manufacturing compliance.

Why is effective cleaning so important in PLP?

Effective cleaning is critically important in PLP because it ensures the removal of flux residues and other contaminants that can cause defects such as shorts, corrosion, delamination, and device failure. PLP uses larger panels compared to traditional wafers, increasing cleaning complexity as residues must be thoroughly removed even in small spaces with high surface tension, such as sub-20-micron bump pitches. Residue left after solder reflow can lead to electrochemical migration, affecting package reliability and yield. Also, cleaning must be uniform across larger panel sizes and varied materials, requiring advanced cleaning technologies, such as vacuum-based and chemical processes, to prevent defects and improve overall HVM performance.

References

1Shilov, A., “NVIDIA’s Next-Gen Blackwell GPUs Rumored To Use Multi-chiplet Design,” Tom’s Hardware, September 2023.

2“TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road,” Global SMT & Packaging, July 2024.

ACM Research, Inc.
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