Challenges with Conventional Chemical Mechanical Polishing
As logic device dimensions continue to shrink, new interconnect materials are required to maintain electrical performance and long-term reliability. Ruthenium (Ru) has emerged as a strong candidate for advanced logic applications, including high-performance computing (HPC) and artificial intelligence (AI). With its superior electrical characteristics and lower diffusion tendency compared with copper (Cu), ruthenium offers the potential to simplify interconnect integration and enable next-generation performance scaling.
At advanced technology nodes, the resistance of titanium and titanium nitride (Ti/TiN) liners and copper increases significantly, leading to higher line resistance and reliability challenges. To address these limitations, ruthenium is being explored as a promising liner and interconnect material for advanced logic devices used in HPC and AI applications. Ruthenium’s resistance and electrical performance are superior to those of copper at dimensions below 17nm; however, its high hardness and chemical inertness present considerable challenges for removal and planarization using conventional chemical mechanical polishing (CMP).
As a result, new process technologies are needed to enable the effective integration of ruthenium into advanced interconnect structures. Leveraging ACM Research’s extensive experience in stress-free polishing (SFP) for metal interconnects, we have developed a specialized process that allows ruthenium to be integrated efficiently into the back-end-of-line (BEOL) flow for leading-edge logic devices.
Ruthenium as an Emerging Interconnect Material
At interconnect dimensions below 17nm, the resistance of copper and the liners, which are used as barrier layers, increases. Copper’s physical and electrical properties lead to higher resistance, which reduces the amount of current that can effectively be run through the interconnect. As a result, the electrical performance does not meet the criteria needed for advanced interconnects in leading-edge logic devices.
Ruthenium’s electrical characteristics are superior to those of copper for interconnect dimensions below 17nm, and it is seen as a possible replacement for copper as technology nodes and dimensions continue to shrink. In addition to ruthenium’s electrical advantages at smaller features, ruthenium is less prone to diffusion in silicon and silicon dioxide (Si/SiO2) and thus does not require a barrier layer or a liner. This simplifies the interconnect process, as only one deposition step is required.
That being said, one of the advantages of copper is that it is easily planarized using CMP technology. Ruthenium, on the other hand, has a higher hardness and a greater chemical inertness, which makes its removal challenging in a conventional CMP process. Therefore, new process technology is needed to more easily integrate ruthenium into the interconnect process. With ACM’s experience in SFP and modifying CMP chemistries to remove challenging films, we developed techniques to create processes for efficient ruthenium removal.
Developing an Efficient Ruthenium Stress-Free Polish
ACM Research has extensive experience using SFP in the interconnect process. After developing a highly successful SFP for copper technology, we set out to develop an integrated SFP and wet-etching process solution for efficient ruthenium removal. Using an electrochemical reaction mechanism, the SFP step modifies the ruthenium surface, forming a thin ruthenium oxide (RuO2) layer. This oxide layer is then etched by a hydrofluoric (HF) acid solution, to which metallic ruthenium shows little or no reactivity. By optimizing the process parameters, an exceptional removal rate exceeding 15Å per second was achieved. Furthermore, fine-tuning the dilute HF (DHF) concentration enabled high removal selectivity between ruthenium and SiO2, which can lead to higher yields due to improved pattern fidelity. The integrated SFP–wet-etch process illustrates great potential to be the process of choice to replace conventional CMP of ruthenium in advanced interconnect applications.
Advancing Logic Process Development
As the interconnect lines continue to shrink, innovative materials and processes will be required to achieve the necessary electrical performance. Moving to ruthenium for spacings below 17nm is one of the key steps for future technology development. ACM Research’s work in developing a highly selective, production-worthy SFP process for the removal of ruthenium demonstrates the forward-thinking approach taking place at ACM Research to find new solutions in advanced logic process development.